Memories are organized in arrays of cells, cells of one and the same column being connected to a bit line and the cells of one and the same row being connected to a word line. The bit line is used to transmit information on the state of a memory cell located at the intersection of this bit line and a selected word line. This information is then processed by a read circuit to determine the state of the memory cell.
In an EEPROM memory, the cells may be in a blank state in which they let through a reference electrical current, an erased state in which they let through a current greater than the reference current or a programmed state in which they counter the passage of a current. To read the information, it is sought to detect the presence of a current flowing in the bit line connected to the cell to be read: a current of this kind is present if the cell is erased or blank. Otherwise it is programmed.
To detect the presence of the current, a reference line similar to the bit line is used. This reference line is crossed by the reference current during a reading phase. This reference current may be provided, for example, by a reference cell. The phase for the reading of a memory cell is preceded by a phase for the precharging of the bit line and the reference line. During this phase, the bit line and the reference line are precharged at a potential of about 1 volt. This potential is limited to 1 volt to prevent any stress on the cells connected to the bit line. During the reading phase, the current flowing in the bit line is compared with the reference current to find out whether the cell read is programmed or erased.
FIG. 1 gives a simplified view of a prior art read circuit. A memory cell CM located at the intersection of a word line LM and a bit line LB is selected by the word line and delivers a piece of information on the bit line. In a conventional way, the memory cell CM includes a floating-gate transistor TGF1 series-connected with a selection transistor TS1. The control gate of the selection transistor TS1 is connected to the word line LM, while the control gate of the transistor TGF1 receives a read voltage during the reading phase. The bit line LB is selected by a bit line selection transistor TSLB. The bit line LB is precharged in voltage during a precharging phase by a precharging transistor T1 which has the function of providing a precharging current to the bit line, while limiting the precharging potential to a determined value of about 1 volt.
A reference line LR whose characteristics are very similar to those of the bit line LB, especially from the viewpoint of the parasitic capacitance, is also precharged at a potential of about 1 volt by a precharging transistor T2. In the example of FIG. 1, the reference line LR is connected to a reference cell CR provided by a selection transistor TS2 series-connected with a floating-gate transistor TGF2.
During the reading phase, a read voltage is applied to the control gate of the transistor TGF2 and the reference line is then crossed by a reference current.
To limit the precharging of the bit line LB and the reference line LR to 1 volt, the transistors T1 and T2 are looped to themselves by inverter gates INV1 and INV2. Thus, the source and the control gate of the transistor T1 are respectively connected to the input and the output of the inverter gate INV1. Similarly, the source and the control gate of the transistor T2 are respectively connected to the input and to the output of the inverter gate INV2. These four elements then form a device to limit the precharging of the lines LB and LR. To obtain the desired precharging potential, the size of the transistors of the inverter gate is determined as a function of the equivalent capacitance of the bit line and of the reference line.
To read the state of the cells, a comparison is made between the current consumed by the bit line and the reference current. More specifically, the current consumed by the bit line is compared with a current that is a fraction of the current consumed by the reference cell.
To do this, the drains of the transistors T1 and T2 are supplied by the two arms of a current mirror having a copying ratio k smaller than 1. The first arm of the mirror has a copying transistor T3 and the second arm has a reference transistor T4. The copying transistor T3 tends to copy the current flowing in the reference transistor T4. Conventionally, the copying ratio is equal to 1/2.
The copying transistor T3 is a P type transistor having its source connected to a supply terminal Vcc and its drain is connected to the drain of a transistor T1. The reference transistor T4 is, in the same way, a P type transistor whose source is connected to the supply terminal Vcc and whose drain is connected to the drain of the transistor T2. The control gates of the transistors T3 and T4 are connected to each other and the gate of the transistor T4 is connected to its drain.
A differential amplifier AD has its inputs connected to the drains of the transistors T3 and T4 and measures the difference between the potentials at these two drains. This difference is zero if the currents flowing in the transistors T3 and T4 have a ratio equal to k. The output of the amplifier AD gives a signal indicating whether the ratio between the currents is greater than k or smaller than k.
The read circuit may have two supplementary transistors T5 and T6 added to it. These transistors T5 and T6 are designed to accelerate the precharging of the bit line and the reference line. These transistors are controlled by a precharging signal PREC that is active during the precharging phase and enables the application of a voltage close to the supply voltage to the drains of the precharging transistors T1 and T2 during the precharging phase.
The main drawback of this type of circuit is that the operation of the precharging limitation device provided by the transistors T1, T2 and the inverters INV1, INV2 is never satisfactory when the supply voltage of the read circuit is low, in the range of 1.8 volts. Indeed, with a maximum voltage (1.8 volts) that is lower at their control gate, the transistors T1 and T2 are less conductive and the control of the current and of the precharging potential becomes less precise. The time taken to precharge the bit line is thereby penalized. Furthermore, since the drain-source voltage of the transistors T1 and T2 is relatively low, their action on the bit line and the reference line is never completely controlled.
It is possible to consider modifying the characteristics of the transistors of the cells of the memory to reduce the borderline value of the precharging potential of the bit lines which is 1 volt.
This approach would make it necessary however to qualify a new technology. This is particularly lengthy and costly.
It is also possible to use large precharging transistors T1 and T2 so that they let through more current and reduce the precharging duration. However, the drain-source voltage of the transistors T1 and T2 would remain the same.